Limitations of VLSI Implementation of Delay-Insensitive Codes

Implementation of delay-insensitive (DI) or unordered codes is the subject of this report. We present two diierent architectures for decoding systematic DI codes: (a) enumeration-based decoder, and (b) comparison-based decoder. We argue that enumeration-based decoders are often impractical for many realistic codes. Comparison-based decoders that detect arrival of a code word by comparing the received checkbits with checkbits evaluated using the received data are practical but suuer from the following limitation. If the decoder is to be implemented using asynchronous logic, i.e., if the gate and wire delays are arbitrary (unbounded but nite), then it is impossible to design a comparison-based decoder for any code that is more eecient than a dual-rail code. In other words, the encoded word must contain at least twice as many bits as the data. The report shows that comparison-based decoders for codes that have the requisite level of redundancy can be implemented using asynchronous logic. The report also shows that, by relaxing the delay assumptions, it is possible to implement decoders for delay-insensitive codes that are more eecient than dual-rail codes.